EDN

Clock Tree Design for Complex Internet Infrastructure

Silicon Labs announced the release of an online timing utility that eases the complexity of designing clock trees for a wide range of Internet infrastructure applications including high-speed ...
Electronic Design

Timing Decisions 102: Optimize Your Clock Tree

The importance of timing requirements and jitter budgets for FPGAs, ASICs, and SoCs. How to utilize the information portrayed in a clock tree to choose the most well-suited clock generator for your ...
EDN

Low Jitter Clock Oscillator

Texas Instruments (TI) rolled out a family of fully programmable, pin-selectable and fixed-frequency 7-mm-by-5-mm differential oscillators that provides the industry’s lowest jitter of 90 femtoseconds ...
Electronic Design

Clock-Tree Tool Supports Internet Infrastructure Designs

An online timing tool crafted by Silicon Labs eases clock-tree design for Internet infrastructure applications. The Clock Tree Expert tool enables fast generation of sophisticated, streamlined ...
Business Wire

Skyworks Unveils Industry’s First Clocks for Ethernet and PCI Express® With 18fs RMS Phase Jitter

The SKY63104/5/6 family of jitter attenuating clocks and SKY62101 clock generators are the industry’s first clock devices that can simultaneously generate Ethernet and PCI Express® (PCIe) spread ...
Business Wire

Skyworks Introduces Best-in-Class Jitter Attenuating Clocks to Address High-Speed Communications’ Timing Requirements

MUNICH--(BUSINESS WIRE)--Skyworks Solutions, Inc. (Nasdaq: SWKS) today launched its latest portfolio of jitter attenuators for high-speed networking, communications and data center equipment forming ...
Semiconductor Engineering

Clocks Getting Skewed Up

At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it’s fraught with the most problems at the ...