Hackaday

Visualizing Verilog Simulation

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some ...
Hackaday

Open Source IDE For FPGAs As QtCreator Learns Verilog

Classic battles: PC vs Mac, Emacs vs Vi, Tastes Great vs Less Filling, and certainly one that we debate around the Hackaday watercooler: command line or IDE? There’s something to be said for using ...
EDN

What’s the best book on how to *structure* an FPGA project?

I just received an email from a reader asking a rather interesting question. His message read as follows: Greetings Mr Maxfield. I have been enjoying your PLDL Newsletter. The personal touches of your ...