EDN

Implementing and Converting Logic Circuits Using Only NAND or NOR Gates

This is going to be a column that’s divided into three sections. It’s based on a question that a student posed in the EEWeb forums, and he also sent it directly to yours truly. The core of this ...
EDN

Less is More When You Design With Configurable and Combination Logic

If you’d like to squeeze more functionality into less space, while simplifying inventory and reducing system cost, then check out NXP’s configurable and combination logic. These flexible and ...
Design-Reuse

Efficient logic optimization utilizing complementary behavior of CMOS gates

Any typical digital design style with CMOS uses complementary pairs of p-type and n-type MOSFETs for logic functions implementation. Naturally, CMOS always ought to provide INVERTED outputs like ...
Electronic Design

Six MOSFETs, Four Pins Create Two-Input Combo NAND/NOR Gate

This CMOS two-input combination NAND/NOR gate is a three-input, fourpin logic gate. A p-channel enhancementtype MOSFET (Q1) and an n-channel enhancement-type MOSFET (Q4) form one complementary ...